This invention relates to address gates for a random access memory, and further to the addressing of such a memory.
In a typical two-transistor address gate, a constant or threshold voltage V.sub.TH is applied to the base of one transistor, while a varying input signal is applied to the base of the other transistor, with complimentary outputs being read at the respective collectors of the transistors. It is common practice in emitter-coupled logic random access memories to use phasing of input timing signals to increase the apparent random access memory speed. In practice, for example, a random access memory may be designed to be addressed at 48 nanosecond intervals, but in order to increase speed, the gate address might be, for example, made to change every 12 nanoseconds. The complimentary outputs of the gate, communicating with a decoder, might then be forced to change readings every 12 nanoseconds. It has been found that the current design of address gates and decoders are able to operate at such speed. However, the random access memory, being designed to operate at a slower speed, cannot respond to this level of speed, which could lead to data errors in the contents of the random access memory.